1. Field of the Invention
The present invention relates generally to a class of transistors based on III-nitride materials, and relates more particularly to enhancement mode III-nitride transistors.
2. Background Art
Transistors based on III-nitride heterojunction structures typically operate using piezoelectric polarization fields to generate a two-dimensional electron gas (2DEG) that allows for high current densities with low resistive losses. The 2DEG is formed at an interface of III-nitride materials and, due to the 2DEG, conventional III-nitride heterojunction transistors typically conduct without the application of a gate potential. Thus, transistors that are formed using III-nitride heterojunction structures tend to be nominally on, or depletion mode transistors.
III-nitride heterojunction transistors are desirable for power applications due to relatively high breakdown voltage, high current density, and low on resistance. However, the nominally on nature of conventional III-nitride heterojunction transistors can introduce problems when used in power applications. For example, in power applications it is desirable to avoid conducting current through III-nitride heterojunction transistors before control circuitry is fully powered and operational. Accordingly, it would be desirable to provide III-nitride heterojunction transistors that are nominally off, or enhancement mode transistors to, for example, avoid current conduction problems during start-up and other circuit conditions.
Thus, there is a need in the art for an effective III-nitride transistor configured as an enhancement mode, or nominally off transistor.